Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier

Riya Jain,Neeta Pandey,Khushbu Pahwa

doi:10.15598/aeee.v19i3.4199

Abstract

There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.

Highlights

Approximate multipliers [1], [2], [3], [4], [5], [6] and [7] have garnered a lot of attention from the researchers in the recent past
We propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier
To further enhance the performance of the existing Karatsuba multiplier, we have proposed the hybridized architecture in which all the smaller size multipliers of Karatsuba algorithm are realized to exploit the advantages of reduced number of partial products obtained from modified Booth algorithm and the fast, parallel addition offered by Wallace Tree structure

Summary

Introduction

Approximate multipliers [1], [2], [3], [4], [5], [6] and [7] have garnered a lot of attention from the researchers in the recent past This is primarily due to the need to develop architectures for arithmetic computing that can reduce delay, power and hardware utilization, while relaxing the constraint on accuracy. Booth and Wallace tree multipliers can be modified and hybridized together to obtain an optimized multiplier, namely Booth-Encoded Wallace tree multiplier This hybrid architecture has been leveraged by several researchers [16], [17], [18], [19] and [20] to attain higher speed and area optimization. Puts forth the background of our research, focusing on Booth’s algorithm, Wallace tree multiplier and how they can be hybridized to obtain an optimized Booth-Encoded Wallace tree multiplier.

Modified Booth’s Algorithm

Booth-Encoded Wallace Tree Multiplier

Proposed Algorithm

Conclusion