Book review

Abstract

Memristors have gained increasing interest recently as emerging memory technologies. Their unique ability to perform logic operations within the memory makes them even more attractive. MAGIC NOR is one such logic gate that can be integrated within memristive memory cells, thus opening possibilities for real in-memory computing. This paper explores the integration of MAGIC NOR gates within large-scale memory crossbar arrays. We evaluate both analytically and numerically different non-ideality parameters that influence the logic gate performance. First, we investigate the effect of parasitic resistance and capacitance within the memory array. Then, process and device variations are considered and modeled, as well as environmental conditions such as temperature and power supply variations. These non-idealities are formulated in the form of process corners that enable designers to estimate the effect of variations on their design in worst case scenarios, similar to the manner in which such effects are estimated in CMOS-based VLSI design.