Abstract
The Probe, a CMOS ASIC (application-specific integrated circuit) that can be used to regain observability lost to higher gate-to-pin ratios and packaging density is described both functionally and technically. This hardware solution will allow board-level designs to look like total boundary scan. The economic feasibility depends on how rapidly present designs move forward: successful application depends heavily on the adoption of P1149.1. The Probe solution offers an opportunity to fuse old and new silicon technologies into a single hierarchical test strategy. >
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