Board Level Reliability Enhancement with Considerations of Solder Ball, Substrate and PCB

Abstract

Solder joint fatigue is a major cause to failure of electronic packages under board level temperature cycling test (TCT). In order to enhance solder joint board level reliability, the trend of industrial solder alloy development has moved towards high mechanical strength and hardness by adding Ag content and doping trace elements, such as Ni and Bi. Both finite element analysis (FEA) and experiment on stacked eight-die flash-memory package have demonstrated that high strength solder ball can perform well against fatigue under TCT. However, the high stiffness and hardness solder balls can generate a noticeable increase of stress and consequently cracking in substrate and printed circuit board (PCB). For instance, trace cracking in teardrop near solder pad has been observed in experiment. Modeling also shows that substrate trace near teardrop can accumulate a considerable amount of plastic strain with high strength solder ball over TCT cycles. It shows similar risk in PCB via with high strength solder ball as well. Thus, it becomes imperative to improve design at these locations of stress concentration manifested by high-strength solder balls. In this work, we introduce some solutions for the application of high strength solder ball to enhance solder joint fatigue performance without adversely affecting the reliability of substrate and PCB. According to the modeling results, the stress concentration at the substrate teardrop between the solder pad and via can be removed by modifying the teardrop shape by either increasing teardrop width or prolonging the distance from via to pad. The enhancement of PCB is to increase the depth of the blind via under solder pad as well as use high-strength PCB laminated dielectric material in case of laminate fracture and pad cratering.