Abstract
The performance of high power packages is limited in part by the interfacial resistance between the die and lid or heat sinks. The thermal resistance depends on the shape of mating surfaces, bondline thickness (BLT) of the thermal interface material (TIM), bulk thermal conductivity and contact resistance. This paper focuses on warpage modeling methods to predict the local variation of TIMs and its impact on thermal resistance as a function of assembly processes. Experimental data and simulations show that when packages are soldered to the motherboard, they tend to have less warpage than unmounted packages. A 17% reduction in thermal resistance was predicted for a bare die package once soldered to the mother board. Close agreement between warpage simulations and experimental measurements is observed.
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