Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation

Abstract

Nowadays, smart devices have been rapidly developed. Most of them are just sensors and actuators without independent computation ability. The devices computation would be done in a device coordinator which need communication time between them. It makes the devices can't respond its input in the right time. Independent computation ability is needed by smart devices. Yet, its implementation has limitation in resource usage and accuracy. One of the problem for the devices accuracy is its number representation for its learning implementation. In this research we propose block and booth floating point number implementation to increase smart devices accuracy with their resource usage comparison. The research resulted FPGA components which could improve previous implemented FPGA algorithm accuracy by 17 % with two alternatives: component with minimal time consumption or component with minimal resource consumption.