Black Box Polynomial Identity Testing of Generalized Depth-3 Arithmetic Circuits with Bounded Top Fan-In

Abstract

In this paper we consider the problem of determining whether an unknown arithmetic circuit, for which we have oracle access, computes the identically zero polynomial. This problem is known as the black-box polynomial identity testing (PIT) problem. Our focus is on polynomials that can be written in the form f(xmacr) = Sigmai=1 k hi(xmacr) ldr gi(xmacr), where each hi is a polynomial that depends on at most p linear functions, and each gi is a product of linear functions (when hi = 1, for each i, then we get the class of depth-3 circuits with k multiplication gates, also known as SigmaPiSigma(k) circuits, but the general case is much richer). When maxi(deg(hildrgi)) = d we say that f is computable by a SigmaPiSigma(k, d, p) circuit. We obtain the following results. 1. A deterministic black-box identity testing algorithm for SigmaPiSigma(k, d, p) circuits that runs in quasi-polynomial time (for p = polylog(n + d)). 2. A deterministic black-box identity testing algorithm for read-k SigmaPiSigma circuits (depth-3 circuits where each variable appears at most k times) that runs in time n2 o(k2) This gives a polynomial time algorithm for k = 0(1). These are the first sub-exponential black-box PIT algorithms for circuits of depth higher than 2. Our results can also be stated in terms of test sets for the underlying circuit model. A test set is a set of points s.t. if two circuits get the same values on every point of the set then they compute the same polynomial. Thus, our first result gives an explicit test set, of quasi-polynomial size, for SigmaPiSigma(k, d, p) circuits (for p = polylog(n + d)). Our second result gives an explicit polynomial size test set for read-k depth-3 circuits. The proof technique involves a construction of a family of affine subspaces that have a rank-preserving property that is inspired by the construction of linear seeded extractors for affine sources of Gabizon andRaz [9], and a generalization of a theorem of [8] regarding the structure of identically zero depth-3 circuits with bounded top fan-in.