Bit-serial systolic array implementation of a multilayer perceptron

Abstract

The paper describes the implementation of a bit-serial systolic array architecture for a multilayer perceptron. It is shown that both the recall phase and learning phase can be mapped onto a similar systolic array structure, with minor differences. As a result, a combined systolic array structure is proposed for both the recall phase and the learning phase. The design is simulated using the FIRST silicon compiler to solve the exclusive OR problem, and then compared with a 32-bit floating-point simulation. The central element, multiply-and-accumulate operator was fabricated using a 1.2 μm double metal CMOS p-well process by ORBIT semiconductor, and found to perform satisfactorily. The required chips were implemented with the same technology, and performance parameters estimated. Furthermore, the performance of this architecture in solving the NETtalk problem is compared with other implementations.