Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM

Abstract

Spin-transfer torque random access memory (STT-RAM) is one of the most promising emerging nonvolatile memory technologies suitable for substituting traditional memory due to its fascinating features, such as high density and low-leakage power. Multilevel cell (MLC) STT-RAM stores two or more bits in a single cell, which can boost data density. Memory partitioning is an efficient method to overcome the impediment of memory bandwidth restricting the speed of parallel data access. However, when applied to previous memory partitioning methods, MLC STT-RAM is still facing challenges. Since these methods have no respect for the issue of read disturbance, the computation performance is unsatisfactory. In this paper, we propose a bit-level disturbance-aware memory partitioning (BaMP) method for parallel data access on MLC STT-RAM. It can effectively eliminate the conflicts between read operations and check operations, which are caused by the read disturbance of STT-RAM, by scheduling the check operations to different time to avoid conflicts. Moreover, bit-level optimization strategies of check merging and check reducing are integrated into the BaMP flow to exploit the MLC STT-RAM structure. The evaluation results on an open data set show that our BaMP outperforms the state-of-the-art method in terms of bank number, storage overhead, performance, and searching speed.