δ-Bit serial binary addition with linear threshold networks

Abstract

In this paper we investigate δ-bit serial addition in the context of feed-forward linear threshold gate based networks. We show that twon-bit operands can be added in\(2\left\lceil {\sqrt n } \right\rceil \) overall delay with a feed-forward network constructed with\(\left\lceil {\sqrt n } \right\rceil + 1\) linear threshold gates and\(\frac{1}{2}\left( {5\left\lceil {\sqrt n } \right\rceil ^2 + 9\left\lceil {\sqrt n } \right\rceil } \right) + 2\) latches. The maximum weight value is\(2^{\left\lceil {\sqrt n } \right\rceil } \) and the maximum fan-in is\(3\left\lceil {\sqrt n } \right\rceil + 1\). We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constantW, twon-bit operands can be added in\(\left[ {\log W} \right] + \tfrac{n}{{\left[ {\log W} \right]}}\) overall delay with a feed-forward network that has the implementation cost [logW]+1, in terms of linear threshold gates,\(\tfrac{1}{2}(5[\log W]^2 + 9[\log W]) + 2\) in terms of latches and a maximum fan-in of 3[logW]+1. We also prove that, if the fan-in values are to be limited by a constantF+1, twon-bit operands can be added in\([\tfrac{F}{3}] + \tfrac{n}{{[\tfrac{F}{3}]}}\) overall delay with a feed-forward network that has the implementation cost\([\tfrac{F}{3}] + 1\), in terms of linear threshold gates,\(\tfrac{1}{2}(5[\tfrac{F}{3}]^2 + 9[\tfrac{F}{3}]) + 2\) in terms of latches, and a maximum weight value of\(2^{[\tfrac{F}{3}]} \). An asymptotic bound of\(O(\tfrac{n}{{\log n}})\) is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order ofO(n). The implementation cost in this case is in the order ofO(logn), in terms of linear threshold gates, and in the order ofO(log2n), in terms of latches. The maximum fan-in is in the order ofO(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented.