Bit-error-rate aware sensing-error correction interaction in spintronic MRAM

Abstract

Internal memories e.g., DRAM and SRAM are partially being replaced by non-volatile memories (NVMs) for the challenges caused by storage capacitance and leakage current at nanoscale feature sizes. Spin–torque transfer magnetoresistive random access memory (STT-MRAM) is a proper non-volatile memory candidate for next-generation main memory on account of low write energy, high speed and high endurance relatively. However, due to imperfect magnetic tunnel junction (MTJ) and array-level density requirement, the failure probability of STT-MRAM becomes a critical issue. The sensing operation suffers from input offset of sensing amplifier (SA), reference distribution and read-disturbance. In order to alleviate the error rate, error-correcting code (ECC) is commonly implemented as a separate module with redundant bit, additional energy consumption and layout overhead. In this paper, we propose a novel cross detected SA-ECC interact design methodology using ECC Galois field compression (GFC), so that the amount of data processing in ECC-GFC is highly depended on the output of SA. Simulation is performed with a 28 nm CMOS process and a 40 nm MTJ compact model. Experimental results show that when SA is with high bit-error-rate (BER), ECC layout area is increased by 1% with GFC. When SA is with low BER, layout area can be reduced by 10%. Under the condition of high and low BER of SA, the maximum power consumption decreases by 10% and 17% respectively compared with the conventional ECC module.