BIT Design of Hierarchical Structure of Avionics System

Abstract

To solve the problem that the BIT system of avionics system is insufficient in testing and isolating power and occupies too many resources, this paper proposes a new distributed hierarchical structureBIT (Built In Test) architecture for avionics system, which only uses monolithic SoC(System on Chip)to build a three-level BIT system of device, module and LRU(Line Replaceable Units). This system creates embedded ATE(Automatic Test Equipment)in module and can carry out boundary scan and signal detection, diagnosis, report, record and processing; it establishes airborne internal detection bus and realizes the transmission of information related to BIT; it uses control command, builds a BIT system independent of device capabilities in master-slave mode and can interact with ATE in off-line state. The experimental results show that the design in this paper is superior to the BIT design technique that traditionally uses FPGA to conduct boundary scan and construct MTM bus and is featured by powerful function, small volume and low cost to become the preferred program of BIT system of avionics system.