Bipolar transistor design for optimized power-delay logic circuits

Abstract

This design optimization scheme provides a procedure for tailoring the impurity doping profile of the transistor so that the performance of the logic circuit can be optimized at a specific power dissipation level and a given lithographic line width. It is shown that the condition of the optimized circuit performance dictates a set of relationships between the transistor structure, the logic voltage swing, and the value of the circuit elements. This paper further discusses the relation between the circuit properties and the transistor size, which becomes smaller as the lithography advances. It is concluded that as the horizontal dimensions are reduced, the vertical dimension of the transistor must be reduced, the impurity density increased, and the current density increased in order to increase the circuit speed. A simple relationship between the lithographic line width and the vertical structure is given which enables one to predict the power-speed performance for the reduced structure.