Abstract

To improve the reliability and system performance many transformation works have been investigated using various contexts. In general, numerical global key models and pseudo-random numbers for public block cipher algorithms suffers from key leakages and insufficient key strength. To overcome all these challenges, an intellectual cryptosystem is proposed with hierarchical hardware pipelined structures. An additional goal of the proposed framework is to enhance the area efficiency, throughput and optimize the hardware structures. In this paper 256-bit AES algorithm proposed with highly optimized hardware units using hybrid resource sharing and modified Key schedule along with optimized Sub bytes blocks, for reduced complexity overhead. The path delay optimization is achieved by decomposing the internal operations into bytes and applied stage wise pipelining and compared with direct 128-bit AES operations without pipeline. The proposed implementation helps in re-using the same hardware in a pipelined fashion which results in improved area efficiency up to 2.8 times and energy efficiency of 22 % over conventional AES crypto system.

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