Abstract

Numerical increment of analog circuits causes power consumption to increase and requires a larger chip area. In designing an analog complementary-metal-oxide-semiconductor(CMOS) vision chip for edge detection, power consumption should be considered. It restricts the number of the edge detection circuit which is based on the edge detection mechanism of vertebrate retina. In this paper, we applied electronic switches to an analog CMOS vision chip for edge detection to reduce the power consumption. Also, we propose a method to implement vision chip with higher resolution, which is to separate pixels for edge detection into a 128×128 photodetector array and a 1×128 edge detection driving circuit array. The capability to minimize power consumption was investigated by SPICE. Estimated power consumption with 128×128 pixels was below 20mW.

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