Binary-decision-diagram-based decomposition of Boolean functions into reversible logic elements

Abstract

A binary decision diagram (BDDs) is a compact data structure used to represent a Boolean function, which facilitates scalable constructions of Boolean functions using reversible logic gates. Motivated by the scalable synthesis approach, this paper proposes an effective scheme for transforming the BDD representation of a Boolean function into a reversible circuit composed by reversible logic elements. Unlike a logic gate, a reversible logic element carries a memory to record a finite number of states. Especially, logic circuits composed by reversible elements can operate in asynchronous mode, thereby no need of a clock signal to drive all elements operating simultaneously.