Bilevel resist process for 1-Gb DRAM reticles

Abstract

As the requirement of the more tightened design rule has emerged, e-beam direct writing and x-ray lithography have been considered as next generation technology. However, due to the rapid development in photolithography, it will be employed in manufacturing 1 Gb DRAM. To overcome present optical lithographic technology, several possible techniques such as deep ultraviolet (DUV), phase shift mask (PSM), off- axis illumination (OAI), optical proximity correction (OPC), and combinations of these methods are considered. The advanced mask technology play a key role in these technologies and the tendency will be dramatically increased in the near future. Although the resolution of 4X reticle for 0.18 micrometer device is 0.72 micrometer, the feature size less than 0.72 micrometer is necessary for wafer process latitude. Therefore, critical dimension (CD) linearity below 0.72 micrometer is needed for 1 Gb reticle, and the minimum resolution less than 0.3 micrometer should be resolved for the OPC patterns. At low acceleration voltage, however, both the CD linearity and the minimum resolution are so severely affected by electron scattering that small beam size, thin resist, and dose correction will be needed for reducing this effect. In order to satisfy the higher resolution, high acceleration voltage system should be employed. In addition as the field size of device increases and process latitude on the wafer decreases, CD uniformity and defect control will be considered more serious than now. In this paper, discussion of the expected technologies, specifications, improvement of the process in manufacturing 1 Gb DRAM reticles are presented.