Abstract
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture is presented. With the BiCMOS dynamic full adder circuit, an 8 × 8 multiplier designed based on a 2μm BiCMOS technology shows a six times improvement in speed as compared to the CMOS static circuit. The speed advantage of using BiCMOS dynamic full adder circuits is even greater in 16 × 16 and 32 × 32 multipliers as a result of the BiCMOS large driving capability for realising the complex Wallace tree reduction architecture.
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