Biased scan of plasma display panel for data voltage reduction

Abstract

This paper proposes a method of reducing the data voltage Vd of plasma display panels (PDPs). The proposed biased-scan method uses two separate ground systems: one for the sustain pulse generator (FGND) and the other for the data address and control systems (CHGND). A dc voltage bias, which is applied between CHGND and FGND during the address period, reduces Vd while preventing the undesired glow discharge induced by a scan pulse only. CHGND is connected to FGND for the first sustain pulse of each subfield, which reduces the time lag of address discharge, but it is separated from FGND for the other sustain pulses to increase the margin of the sustain voltage. The proposed method was tested on a 15% Xe 50-in. Full HD (1920×1080) single-scan PDP which had a sustain discharge gap of 110μm. Vd could be reduced by 20V (30%), and the power consumption of the Vd voltage source decreased by ∼25W (50%) from that of the conventional method.