Abstract
This paper presents an advanced measurement method for controlling the surface charge carrier density of passivated silicon wafers during photoconductance and photoluminescence measurements, by employing semitransparent poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) electrodes with an applied bias voltage. This is employed to study and analyze charge carrier dynamics in dielectric layers by measuring their direct influence on effective lifetime. With this method, the carrier population at the surface and the effective carrier lifetimes of n- and p-type samples can be investigated, from which the fixed charge carrier density Qf of the passivation can be extracted. Additionally, the defect density Dit can also be derived from the minimum lifetime values at flatband voltage. In SiO2/Al2O3 stacks with varying SiO2 interlayer thickness, it was shown that by changing the SiO2 thickness, the carrier density Qf can be tuned to a wide range of values, which corresponds to the results obtained in other studies. An increase in interlayer thickness resulted in a decrease in Qf. Varying the SiO2 thickness, the behavior of the respective effective lifetime under bias voltage also changes, exhibiting hysteresis-like effects, which are attributed to additional charges getting trapped at the surface during bias-voltage application. This effect is much more pronounced for samples with a thinner SiO2 layer as well as for the n-type samples. Additionally, the doping type also influences the magnitude of Qf, with p-type samples generally reaching lower absolute values. It was also shown that aging of the samples had a significant effect on the measured Qf, which was increased compared to the initial Qf of the passivation. This effect was more pronounced for the n-type samples. The measurements were realized by a cost-effective and easy-to-use microcontroller-based potentiostat, which can be used as a simple add-on to existing photoconductance or photoluminescence measurement setups.
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