Bias temperature instability assessment of n- and p-channel MOS transistors using a polysilicon resistive heated scribe lane test structure

Abstract

A fast wafer level device reliability stress at elevated temperatures is demonstrated. It neither needs an external heat source like a thermal chuck or an oven nor cooling. The necessary temperature for acceleration of the bias temperature stress drift mechanism is achieved by electrically resistive heating. For this reason a polycrystalline silicon (polysilicon) resistive heated test structure was designed with a MOSFET embedded between two polysilicon heater strips. A 4-terminal metal resistor above the heater allows temperature control via the temperature coefficient of the resistance. The stress algorithm performs simultaneous thermal and electrical stress. The device temperature is determined by a comparison of the temperature measured at the metal level and the pn-junction temperature determined from the forward diode characteristics. Results of an assessment of the bias temperature instability of CMOS transistors using this type of structure are discussed. They demonstrate the usefulness of the whole methodology presented.