Abstract
In the present contribution, we have measured and simulated room temperature bias- and frequency-dependent capacitances of thin-film solar cell devices. The results of both the simulations and experimental measurements are represented as 2-D contour plots showing the derivative of the capacitance with respect to the frequency multiplied by the frequency. These plots are called “loss maps,” because responses in these contour plots correspond to responses of different nonidealities in the devices. Using a 1-D drift-diffusion solver (SCAPS), we have simulated the responses of different nonidealities of the solar cell devices, such as series resistance, bulk defects, interface defects, back contact barrier, and absorber–buffer barrier. We have shown that some nonidealities have a quite recognizable trace in the loss map. Other nonidealities on the other hand show responses that look quite similar in the bias voltage and frequency space, making exact conclusions on the nature and position of the defect responses in thin-film solar cells most of the times difficult. We have compared the simulated results with experimental measurements of one of our Cu(In,Ga)Se2 (CIGS) solar cell devices and came to the conclusion that there is likely a bulk defect or a spike-like barrier at the CIGS–CdS interface present in our particular device. The loss map can, in some cases, be useful in order to analyze admittance spectroscopy data in a graphical and relatively intuitive way.
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