Abstract
The total ionizing dose (TID) response of double-gate SiGe- SiO 2 /HfO 2 pMOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the HfO 2 layer, in contrast to what is typically observed for devices with SiO 2 or HfO 2 gate dielectrics. This occurs in the devices because radiation-induced holes that are generated in the SiO 2 interfacial layer can transport and become trapped in the HfO 2 under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the SiO 2 interfacial layer can transport into the HfO 2 and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias.
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