Beyond time optimal performance using SIMO DC-DC converters in dynamic voltage scaling

Abstract

Dynamic voltage scaling (DVS) is an useful technique to optimize performance and efficiency of CMOS digital processors using DC-DC converters that require to meet extremely fast slew rate demand. This paper formulates time optimal performance of existing buck-derived DVS architectures, such as using (a) a synchronous buck converter, (b) a multi-phase buck converter, and (c) multiple dedicated buck converter topologies. Thereafter, time optimal performance is formulated using a single-inductor-multiple-output (SIMO) buck converter based DVS architecture. It is shown that a SIMO-derived DVS architecture can achieve performance much beyond system physical limits of that using existing architectures for a step-change in the reference voltage and/or the load current. The proposed architecture and existing power converter architectures are fabricated, and time optimal control is implemented using an FPGA device. Test results demonstrate significant reduction in time and energy overheads using the proposed DVS architecture.