Abstract
Cell disturb is an essential limiting factor in scaling NAND flash devices, which results in interference failures and reduced cell reliabilities. In this study, we compared the Planar(2D) versus Vertical(3D) NAND flash structure and characteristics and found that cell transistor disturb makes the integration limit of 2D NAND flash structure become the improvement in 3D NAND flash structure innovatively. The 3D structure and charge trap flash (CTF) cause the result of innovative not only cell disturb but also excellent data retention. Furthermore, we suggest a design standard for the next generation of 3D NAND flash cell transistors from cell disturb and retention. Figure 1
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