Abstract
This paper presents a low complexity interleaver design that facilitates high throughput Turbo decoding required for next generation wireless systems. When a parallel decoder structure is considered, interleaver design is the most important issue. In such parallel decoder, the contention problem occurs when more than one extrinsic value references to the same memory block for read or write purpose. This paper focuses on the alternate method for QPP interleaver which shows improved BER performance for large frame size. Bit reversed indexing is used to generate interleaved addresses. A counter is used to generate sequential address as well as interleaved address. The number of address lines of memory which stores data , depends upon frame size of data. In this paper, a comparison is made between best proved interleaver and proposed interleaver on the basis of BER performance for different number of iterations, different frame size and different decoding algorithms. General Terms Interleaver, Turbo Decoder, Bit reverse indexing.
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