BER analysis and MAI cancellation in CDMA communication system

Abstract

Authors, in this paper, present a bit error rate analysis and FPGA implementation of multiple access interference cancellation in Code Division Multiple Access (CDMA) communication systems. The main objective of paper is focused on designing and then testing the performance of CDMA circuits implemented on FPGA. Main performance parameter of BER was chosen for simulation. The test performances are analyzed by simulating a CDMA communication system with QPSK modulation and demodulation. The latest technology advancement in cellular mobile communication systems has become more demanding for better quality of service. It requires broad bandwidth for huge quanta of data transfer. CDMA communication system easily meets these requirements of cellular communications. The design of the relevant circuits is based on CDMA approach of direct sequence spread spectrum technology. The functional performance of designed circuits is tested by carrying out simulations using Field Programmable Gate Arrays (FPGA) and Very High Speed Integrated Circuits Hardware Description Language (VHDL) on XILINX ISE <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> and MATLAB <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> platforms. The simulated results subsequently have shown quite improved and optimized circuit performance.