Abstract
The limits and impact of N- and P-channel DMOS voltage scaling on DC/DC conversion efficiency using a synchronous buck topology are explored. In the absence of parasitic resistance, specific on-resistance is found to maintain the well-known BV/sup 2.5/ power law despite a mobility and avalanche field concentration dependence below 100 V. The influence of substrate resistance in voltage-scaled N- and P-channel vertical DMOS is shown to become significant below 40 V, suggesting a limit of 0.076 m Omega -cm/sup 2/. Using DMOS voltage scaling, the conduction losses in a synchronous buck converter having a P-channel switch are found to be lower than those of an all N-channel flyback converter for inputs up to 30 V. For a 6-V input, the buck converter is shown to exhibit a 2* advantage in converter resistance over the flyback topology. A surface-mount chip set combining an optimized low-voltage complementary DMOS half-bridge with a monolithic buck-converter/synchronous-rectifier control IC is shown to achieve efficiencies as high as 97%. >
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