Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Daniel Nagy,Natalia Seoane,Guillermo Indalecio,Antonio J Garcia-Loureiro,Karol Kalna,Gabriel Espineira

doi:10.1109/access.2020.2980925

Abstract

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( $L_{\textbf {G}}$ ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrodinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to $L_{\textbf {G}}$ of 16 nm offering a larger on-current ( $I_{\textbf {ON}}$ ) and slightly better sub-threshold characteristics. Below $\text{L}_{\textbf {G}}$ of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( $I_{\textbf {OFF}}$ ), and the largest $I_{\textbf {ON}}/I_{\textbf {OFF}}$ ratio out of the three architectures. However, the NW FET suffers from early $I_{\textrm {ON}}$ saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

Highlights

Fin field effect transistor (FinFET) technology is the leading architecture for high performance (HP) applications
The overall performance enhancement is compared through the ION/IOFF ratio and we found that it decreases by −32%, −68% and −76% for the NW FET, NS FET and FinFET, respectively, as we increased the NS/D from 5 × 1019 cm−3 to 1.5 × 1020 cm−3
The NS FET can be an excellent alternative to the FinFET for various digital applications because it offers a higher ION and slightly better sub-threshold region characteristics while reusing a similar fabrication process

Summary

INTRODUCTION

Fin field effect transistor (FinFET) technology is the leading architecture for high performance (HP) applications. Three parameters were adjusted: (i) the maximum source/drain doping (NS/D), (ii) the position (Xmax) where the doping starts to decay from NS/D, and (iii) the Gaussian lateral straggle (σmax) This process is repeated until a good agreement is achieved in ID-VG characteristics between the experimental and the simulated data in the sub-threshold region obtained from the 3D SCH-DD. The characteristics are directly obtained by time consuming SCH-MC simulations of electron transport in the transistor domain including electrons in the heavily doped source/drain that provides a correct electron distribution for their injection into device channel [17], [33], [36]. An increase in NS/D affects the performance of the FinFET the most, leading to the worst sub-threshold characteristics and the lowest ION

INTERFACE ROUGHNESS

Findings

CONCLUSION