Abstract
In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.
Highlights
The most significant design challenge in current and future wireless devices is to support several wireless and cellular standards in the same handheld device
Contrary to several multistandard Zero-IF architectures proposed in literature which use channel selection in analog domain and use an automatic Gain Control (AGC) to decrease Analog to Digital Converter (ADC) dynamic requirement [10,11], in our selected multistandard receiver, channel selection is performed in the digital domain and a very high dynamic ADC is used to eliminate the need for AGC
These VHDL-AMS Simulation results show that added to the proposed multistandard modulator which can tolerate an Operational Tranconductance Amplifier (OTA) dc gain of 60 dB, the OTA bandwidth needs to be at least 200 MHz and the slew rate at least 200 V/μs
Summary
The most significant design challenge in current and future wireless devices is to support several wireless and cellular standards in the same handheld device. The noise shaping and the oversampling performed by ΣΔ modulators allow to achieve high Dynamic Range (DR) for narrow bandwidths and lower DR for higher bandwidths This characteristic is coherent with wireless standards requirements and their RF specifications which makes ΣΔ ADC suitable to perform the Analog/Digital (A/D) conversion function in a multi-standard capable RF receiver [7]. Contrary to several multistandard Zero-IF architectures proposed in literature which use channel selection in analog domain and use an automatic Gain Control (AGC) to decrease ADC dynamic requirement [10,11], in our selected multistandard receiver, channel selection is performed in the digital domain and a very high dynamic ADC is used to eliminate the need for AGC
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