Behavioral array mapping into multiport memories targeting low power

Abstract

Off chip memories are typically used during behavioral synthesis to store large arrays that do not fit into on-chip registers. An important power-optimization problem that arises in this context is the minimization of signal transitions on the off-chip buses connecting the ASIC and the memory. We address the problem of system power reduction through transition count minimization on the multiported, memory's address buses when these arrays are accessed from memory at execution time. We exploit regularity and spatial locality in the memory accesses and determine a power-efficient mapping of behavioral array references to physical locations as well as ports of a multiport memory. Our experiments on several image processing benchmarks show significant power savings through reduced transition activity on the memory address buses, compared to a straightforward mapping scheme.