Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing

Abstract

This paper proposes a behavior model for comparator-based switched-capacitor (CBSC) circuits by using SIMULINK platform. In this model, the maximum available time is compared with the charge transfer time required in the CBSC circuit to identify whether the currents chosen are suitable or not. The model is efficient to determine the values of the coarse charging current and the fine charging current required for CBSC circuits in a sigma-delta modulator (SDM). To verify the behavior model, a 3rd order SDM which still retains a half of the clock cycle for quantization and dynamic element matching (DEM) is proposed and simulated. The simulation result shows that the value of SNDR achieves 82.23 dB when the sampling rate is 100 MS/s (OSR=16).