Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units

Abstract

This paper presents a battery-efficient task execution methodology on reconfigurable computing (RC) Platforms which have multiple processing units. These processing units can be on-chip in the form of soft-processors, embedded processors or Reconfigurable Tiles where the reconfigurable area of an field programmable gate array (FPGA) is divided into fixed reconfigurable slots. Processing units can also be off-chip in the form of individual FPGAs and voltage-scalable processors. An application is modeled in the form of a precedence task graph. We assume that for each task in the task graph several different design-points are available which correspond to different voltage-frequency combinations for processors and different hardware implementations for FPGAs and Reconfigurable Tiles. It is assumed that performance and total power consumption estimates for each design-point are available for any given implementation, including the peripheral components such as memory and display power usage. First we present an iterative heuristic algorithm for a single processing unit, which finds a sequence of tasks along with an appropriate design-point for each task, such that a deadline is met and the amount of battery energy used is as small as possible. Next, we extend this algorithm to multiple processing units in an RC platform. We used several real-world benchmarks to test the effectiveness of this methodology. Each benchmark was executed on one, two, three and four processing units and its power utilization was characterized by implementing it on a portable RC Platform called iPACE-VI. We present the results which show that choosing an appropriate execution mode is crucial for battery-efficient execution. We also show that parallel execution on multiple-processing units can actually be more battery-efficient than sequential execution on a single processing unit under certain circumstances.