Bandwidth-enhanced photopolymer waveguide hologram-based optical backplane

Abstract

As multiprocessing comes into the mainstream, the board-to-board interconnects become even more critical. In a shared-memory multiprocessing system, the shared bus topology is the preferred interconnect scheme because its broadcast nature can be effectively utilized to reduce communication latency, lessen networking complexity, and support cache coherence. In the electrical domain, however, a major performance bottleneck is anticipated due to the restricted bus bandwidth. In this paper, an innovative architecture, optical centralized shared bus, is proposed for use in the multiprocessing systems. This architecture utilizes the terascale bandwidth capacity of substrate-guided optical interconnects, while at the same time, retaining the essential merits of the shared bus topology. Thus, a smooth migration with substantial multiprocessing performance improvement is expected. A conceptual emulation of the shared-memory multiprocessing scheme is demonstrated on a generic PCI subsystem with an optical centralized shared bus. The objective of this effort is to prove the technical feasibility from the architecture standpoint.