Bandwidth-Aware High-Efficiency Video Coding Design Scheme on a Multiprocessor System on Chip

Abstract

H.265/high-efficiency video coding (HEVC) provides a multitude of video data compression to minimize data storage and data transmission while preserving video coding quality and ameliorating coding bit rates. However, HEVC encoder chips are frequently integrated into mobile multiprocessor system-on-chip (MPSoC) systems that adopt intelligent thermal and power management techniques for heat- and power-dissipation reductions. Consequently, the accessible coding bandwidth (CB) for HEVC encoder chip use is not fixed, and the compressed video data for data transmission within MPSoCs are restricted to time-altering wireless transmission bandwidths (TBs). Therefore, the proposed bandwidth-aware H.265/HEVC controller design solves the video coding problems of limited CB and TB by jointly using a machine-learning method and convex optimization. The ancillary experimental and implementation results demonstrate that the proposed CB-TB rate-coding distortion (CB-TB-R-D) algorithm modeling and the very large-scale integration (VLSI) hardware architecture are applicable for CB- and TB-constrained HEVC encoder design within MPSoC.