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Abstract
In this paper, we present a bandwidth enhancement technique for monolithic microwave integrated circuit (MMIC) Doherty power amplifiers (DPAs) in wireless transmitters. A broadband load modulation network is proposed by exploiting transformers and output-referred parasitic capacitances of the carrier and peaking transistors of DPA. The proposed network comprises two transformers that are used to improve frequency response of the load impedance presented to the carrier transistor at back-off and extend the DPA bandwidth. The network benefits from a unity transformation ratio and it can be readily realized by using edge-coupled microstrip transmission lines. Optimal coupling coefficients of the two transformers are determined based on bandwidth and insertion loss considerations. A proof-of-concept DPA is implemented in a 0.25-μm GaN MMIC process. It achieves 35-36 dBm output power, 42.8-48.7% drain efficiency at peak power and 24.4-31.6% at 6-dB back-off, over 4.5-6.0 GHz bandwidth. When excited by a 100-MHz 64-QAM signal with 8 dB peak-to-average power ratio (PAPR), the DPA exhibits 29.3 dBm average output power and 28.4% average drain efficiency, while the error vector magnitude (EVM) is -30.5 dB (3%) without any predistortion.
Highlights
The fifth generation (5G) of wireless networks is under advanced development and extensive research activities and trials are ongoing to achieve its targeted expectations
We propose a bandwidth enhancement technique for monolithic microwave integrated circuit (MMIC) Doherty power amplifiers (DPAs) using a transformer-based load modulation network
The chip is wire-bonded to a test printed circuit board (PCB)
Summary
The fifth generation (5G) of wireless networks is under advanced development and extensive research activities and trials are ongoing to achieve its targeted expectations. Most notable bandwidth enhancement techniques developed for DPAs include modified characteristic impedance of transmission lines in the load modulation network, modified network for the peaking transistor, parasitic capacitance compensation, frequency response optimization, and dual-input DPA architecture [3]. Most of these solutions are only applicable to discrete circuits. Using the broadband DPA architecture, bandwidth at back-off is improved to 72% (i.e., by the factor of 1.89)
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