Abstract
The authors present a new multiprocessor model using multiple bus as the interconnection network. In this model N processors, B buses, and M memory modules are connected in groups. The collapse of one or more of those memory modules, processors, and buses can lead to loss in system performance, if not complete collapse. The authors present what they call the graceful degradable scheme for the reconfiguration of processors. Thus the system becomes a multiple-group-multiple-bus system. The bandwidth of every multiple-bus system is calculated and summed together for the calculation of the entire system bandwidth. The average processor-blocking probability is also computed for the individual groups and then added together for the whole system.
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