Balancing of Peak Currents Between Paralleled SiC MOSFETs by Drive-Source Resistors and Coupled Power-Source Inductors

Abstract

The peak currents between two paralleled SiC MOSFETs could differ significantly due to the mismatch in threshold voltages $V_{{\rm{th}}}$ . The method described herein employs passive compensation (drive-source resistors and coupled power-source inductors) to balance the peak currents using one gate driver, no sensors, and no feedback—without increasing total switching loss when equivalent gate-drive resistance $(R_{g} + 0.5R_{k})$ is kept constant. This solution works for both polarities of $V_{{\rm{th}}}$ mismatch and forces balancing from the first current peak. The extra voltage stress from this solution is mitigated by negative coupling. The passive components (resistance, self-inductance, and mutual inductance) are determined by an equation involving the magnitude of $V_{{\rm{th}}}$ mismatch, current rise time, and unbalance percentage. The influence of other parasitic inductances on current sharing is analyzed. The robustness of this passive balancing method is experimentally verified by a prototype with a significant amount of parasitic inductances. Test results show that the difference of peak currents can be reduced from 15% to 3% without changing the switching loss and voltage stress.