Balanced Application Scheduling for Process Variation Influenced Chip Multiprocessors

Abstract

Within-die process variations in chip-multiprocessors cause wide variation in the distribution of frequency and power consumption between similar cores. In such condition, considering variations in task allocation and power management algorithms is crucial. Among various methods proposed to improve performance and reduce power consumption in variation-influenced chip-multiprocessors, two of them are more popular: variation-aware application scheduling and per-core dynamic voltage and frequency scaling (DVFS). However, none of the proposed methods guarantees load balancing in chip-multiprocessors and as a result, appropriate distribution of power in task allocation cannot be achieved by these methods. In this paper we propose an algorithm which intelligently maps (and remaps) applications into cores considering their variations. Moreover, proposed power management algorithm maximizes the overall performance at a given power budget. For power management, low resolution DVFS is used to decrease algorithm overhead. Additionally, the algorithm is “balanced” to avoid hotspots on the chip. The proposed method is tested on a special-purpose simulator based on E3S data-set Experimental results show that the algorithm achieves significant improvement in terms of power distribution and fair application scheduling compared to the other methods.