Abstract
In this work, failure analysis (FA) challenges and new failure modes for devices of copper technology, especially for circuit-under-pad (CUP) devices are presented. Backside FA techniques including backside sample preparation, backside defect localization, backside physical analysis with both deprocessing and cross section analysis have been developed and applied to Cu/low k technology. For backside FA deprocessing, we present wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the backside FA cross-section analysis of copper/low k samples, focused ion beam (FIB) techniques that have been developed and studied are addressed. In addition, detailed characterization of backside silicon thinning using TMAH wet chemicals is presented.
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