Backplane test bus applications for IEEE Std 1149.1

Abstract

Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Providing accessibility and controllability for board testing was simply a matter of probing the board. With the advent of surface mount packaging, the accessibility for probing printed circuit boards began to diminish. Logic cores being integrated onto chips made them inaccessible as well. One of the solutions to address this problem eventually became standardized and is defined in IEEE STD 1149.1. On the printed circuit board level, this standard has become widely used. The classic method of probing boards at accessible test points is still widely used as well, and there are often hybrid test solutions that leverage both bed-of-nails testing and the IEEE STD 1149.1 standard test bus. Decisions for whether or not to use one versus the other are predicated on cost and familiarity with the techniques and architecture. The scope of this paper addresses the application of the IEEE STD 1149.1 test bus standard for system-level applications, which are considered to be systems with multiple printed circuit boards in a backplane configuration. This paper deals specifically with implementations of IEEE STD 1149.1 in a backplane architecture and compare them with some of the other common methods of backplane testing.