Back-End-of-Line and Micro-C4 Thermal Resistance Contributions to 3-D Stack Packages

Abstract

The objective of this paper is to understand and quantify the additional thermal resistance of 3-D stacked packages due to the back-end-of-line (BEOL) layers and die-to-die interconnects, specifically micro-C4s. Of particular interest were the impacts of through silicon vias (TSVs), interfacial thermal resistances between BEOL material layers, and mechanical strain. The study revealed that the TSVs could be effective in reducing overall thermal resistance given an adequately small pitch, alignment with micro-C4s, and penetration through the BEOL layers. A review of theoretical and experimental studies by others revealed vastly different results for the interfacial thermal resistance between material layers, such as in BEOL layers. Theoretical studies suggested 1-2 orders of magnitude lower thermal resistance than experiments. Analysis of the mechanical strain suggested a difficult to quantify but negligibly small impact on the thermal resistance of BEOL layers.