Back-Annotation in High-Speed Asynchronous Design

Abstract

This paper presents the next step in an evolving back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools. This paper demonstrates that these cells can be efficiently modeled in Verilog, effectively characterized in the standard Liberty format, and support accurate Verilog back-annotation using the standard-delay-format (SDF) flow, thereby enabling digital simulation-based performance and timing verification. Experimental results on several test designs including a 260K transistor parallel prefix 64 bit adder design demonstrate the proposed back-annotation flow yields less than 5% error compared with much more time-consuming analog-level simulation using a circuit simulator.