Axon: a host-network interface architecture for gigabit communications

Abstract

As increasing processor power and memory availability allow more demanding applications (such as scientific visualisation and imaging), there is the potential for their support in a distributed environment with the high performance and functionality of emerging networks. However, the bottleneck is increasingly in the host-network interface, and therefore the ability to deliver high performance communication capability to applications has not kept up with the advances in computer and network speed. This research is targeted at solving this problem with the design of a new host communication architecture called Axon, whose novel aspects include: (1) an integrated design of hardware, operating systems, and communication protocols; (2) support for virtual shared memory in a wide area network environment; (3) the proper division of hardware and software communication function; (4) and a pipelined network interface between the network and host memory with no per packet buffering. An extensive simulation model of the Axon architecture has been constructed to evaluate the overall performance, the behavior of the error and flow control mechanisms, and the partitioning of function between hardware and software.