Avoiding loading effects and facet growth: Key parameters for a successful implementation of selective epitaxial SiGe deposition for HBT-BiCMOS and high-mobility hetero-channel pMOS devices

Abstract

The use of selective epitaxial growth for the implementation of SiGe to improve device performance has several advantages compared to non-selective growth. However, some issues such as thickness non-uniformity (micro-loading on μm scale and gas depletion on wafer scale) and facet formation have to be solved. We give an overview of our selective epitaxial SiGe growth process in a standard production Chemical Vapor Deposition (CVD) reactor, and for Ge contents between 0 and 32%. Our process allows to deposit layers with no pattern dependence on growth rate and Ge content (no micro-loading) and with very high cross-wafer uniformity (standard deviation <2%). Facet formation is avoided by choosing the correct growth conditions, and by preventing lateral growth over the mask material. The combination of excellent layer quality, facet-free growth, and the proven layer uniformities permit a successful implementation of SiGe in device technologies as demonstrated by the performance of SiGe BiCMOS (0.25 and 0.35 μm), and p-type hetero-MOS devices ( L poly down to 50 nm).