Avalanche photodiode with high responsivity in 0.35 μm CMOS

Abstract

The presented linear mode avalanche photodiode (APD) uses the standard layers and process steps available in the 0.35-μ m Si bulk CMOS process. Due to a low-doped epitaxial layer with a resistivity of 664 Ω cm , a deep intrinsic zone is realized to enable a large depleted absorption region at already moderate bias voltages and therefore ensures a high low-voltage responsivity. In combination with avalanche gain at high bias voltages, this leads to an overall responsivity of 1.7×10 5 A/W at 1.1 nW optical input power and 670-nm wavelength. The maximum achieved avalanche gain was 4.94×10 5 . The maximum −3 dB frequency of 700 MHz was measured at a reverse bias voltage of 30 V and an optical input power of 14.7 μ W.