Abstract
The era of the Internet of Things comes with a huge number of interconnected communicating devices, which are often rather limited on the energy supply (e.g. battery powered or energy harvesting). Therefore, the pressure on energy efficiency of their operation (influencing lifetime or amount of functions) is especially crucial. In spite of a growing number of IoT devices, there still are many applications that are very specific and their market is quite limited. This is where the FPGAs offer a good alternative to dedicated application-specific chips, which would be too costly for such a purpose. Therefore, we target the power-management automation that simplifies energy-efficient design for FPGA platforms. A designer is then able to specify just an abstract power management in the commonly used SystemC model and it is automatically transformed in the more-complex form acceptable by a specific FPGA device. The proposed simplification and automation shortens the time-to-market of energy-efficient IoT products and prevents possible human-errors that could be otherwise introduced to the design. The alleviated verification and debugging spare even more time in the development process. The experiments have proved the benefits of the proposed automation method.
Highlights
The market forces regarding cost reduction and timeto-market of the products increase popularity of the FPGA (Field-Programmable Gate Array) devices
We extend our previous results [1] into a new method, which enables to analyze the abstract ESL specification of the power-managed system described in SystemC/PMS [26] and automatically synthesizes Verilog model of the power-management unit (PMU) that enables to scale the frequency of the system, as well as other required logic, such as synchronization elements between clock domains of the system
The second part has verified the ability of the tool to create a PMU, including the power-reduction techniques available on the selected FPGA device, based on the extracted power-management information
Summary
The market forces regarding cost reduction and timeto-market of the products increase popularity of the FPGA (Field-Programmable Gate Array) devices. We extend our previous results [1] into a new method, which enables to analyze the abstract ESL specification of the power-managed system described in SystemC/PMS [26] and automatically synthesizes Verilog model of the PMU that enables to scale the frequency of the system, as well as other required logic, such as synchronization elements between clock domains of the system.
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