Automatic Solder Joints Layout Algorithm Based on Electrostatics Model

Abstract

Currently, there are many automated algorithms for solder joints layout, such as genetic algorithms, ant colony algorithms, and neural network-based algorithms. The goal of these algorithms is to find the best solder joint layout to improve the quality of welding. However, due to the limited space in mobile phones, sandwich boards are widely used, and their structure determines that the number of solder joints should be increased as much as possible to enhance the flexibility of the device layout. This article proposes an automatic solder joint layout algorithm based on the electrostatics model for the solder joint layout problem on PCB frame boards and LGA boards. The solder joint and frame board are mapped as charged bodies. The position of each solder joint is continuously iteratively corrected so that the total potential energy of the system is zero, thereby satisfying the constraints to obtain a reasonable layout of the solder joint and increase the number of solder joint layouts. Experimental results show that this algorithm can achieve the maximum automatic layout of solder joints on PCB frame boards and LGA boards, and the space utilization rate can reach 95.5% of the theoretical maximum value.