Automatic refinement of requirements for verification throughout the SoC design flow

Abstract

This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic System Level (ESL) description style, and languages such as SystemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for SystemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples.