Abstract
This paper proposes an optimization approach for an automatic buck converter printed circuit board (PCB) design regarding the electromagnetic compatibility (EMC) constraints. The proposed solution is based on the combination of a genetic algorithm (GA) and a Dijkstra algorithm to generate the different PCB layout designs. Afterwards, a numerical modeling approach, taking into account all the stray elements, is proposed to obtain an accurate equivalent circuit for the PCB layout using ANSYS Q3D software. Subsequently, the complete behavior of the converter is simulated within SIMPLORER, including the electrical models of the components, the Line Impedance Stabilization Network (LISN) module as well as the PCB layout model. This aims to compute the conducted disturbances such as the common and the differential mode voltages. Then, this approach is implemented in an optimized process to reach the optimal geometry for the printed circuit board layout with the lowest parasitic effect to fit the EMC requirements. Finally, measurements are performed, and the optimization results are presented and investigated, in comparison with reference PCB layout to assess the efficiency of the proposed methodology.
Highlights
With the current evolution of electronics, the development of power electronics systems takes a very prominent place in various applications such as the automobile and aircraft applications
The optimization parameters of printed circuit board (PCB) layout are gathered in the vector Xi where the number of variable is 15
The optimization process tested 1500 different PCB layout solutions to obtain the optimized solution presented in Figure 17 (a)
Summary
With the current evolution of electronics, the development of power electronics systems takes a very prominent place in various applications such as the automobile and aircraft applications. Mandray et al [14] presented thermal and simple EMC models to realize an automatic layout design of a double-sided power module without considering time and accuracy. These models include thermal effects and parasitic capacitors while inductance has been ignored. Work described in [15] used a GA for layout optimization of a simple power module to minimize parasitic elements With this method, the computational population increased significantly due to all possible designs being considered. Our aim is to develop an automatic optimization process for a dc-dc converter PCB layout in order to reach the best solution respecting a reduced EMC signature. In order to model the Schottky diode SC250KG, we used the model provided in the SIMPLORER software library
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